In a digital radio communication system, transmission quality (such as a bit error rate and throughput characteristics) depends on a radio wave propagation environment such as fading and shadowing, and transmission data transmitted by a transmitter apparatus might be received as erroneous data by a receiver apparatus.
In consideration of such circumstances, the digital radio communication system uses an error control technique for allowing the receiver apparatus to receive correct transmission data even in a poor radio wave propagation environment.
The error control technique is a technique of reducing the probability of bit error occurrences in the transmission data and of realizing a radio communication system having higher transmission quality even using the same received power.
Here, the error control technique can be roughly classified into forward error correction (FEC) processing and automatic repeat request (ARQ) processing.
Note that error correction encoding processing can be cited as the FEC processing. Specifically, in the error correction encoding processing, redundant bits are added to a bit sequence of transmission data according to a certain rule, thereby allowing restoration of bits erroneously received due to a radio wave propagation environment.
A receiver apparatus adopting the ARQ processing is configured to determine whether or not received data is correct and to send a retransmission request back to the transmitting side when an error is detected.
Here, FIG. 1 shows configurations of a transmitter apparatus 10 and a receiver apparatus 30 in a radio communication system using both ARQ processing and FEC processing.
As shown in FIG. 1, the transmitter apparatus 10 includes a transmission data generator unit 11, a CRC adder unit 12, a divider unit 13, an error correction encoder unit 14, an interleaver 15, a modulator 16, and a transmission controller unit 17.
Meanwhile, the receiver apparatus 30 includes a demodulator 31, a deinterleaver 32, an error correction decoder unit 33, a connector unit 34, a CRC checker unit 35, and a received data acquirer unit 36.
As shown in FIG. 2, in the transmitter apparatus 10, the transmission data generator unit 11 generates transmission data (a bit sequence). In Step S1001, the CRC adder unit 12 performs error detection encoding processing using a CRC (Cyclic Redundant Check) code and thus adds the CRC code (a parity bit sequence) to the transmission data (the bit sequence) in order to perform error detection processing in ARQ processing.
In Step S1002, the divider unit 13 divides the transmission data (the bit sequence) to which the CRC code (the parity bit sequence) has been added into encoded bit sequences #1 to #9 in units (bit size) for performing error correction encoding processing.
In Step S1003, the error correction encoder unit 14 performs the error correction encoding processing on the multiple encoded bit sequences #1 to #9. As a result, encoded bit sequences #A1 to #A9 to which redundant bits have been added are obtained.
In order to randomize errors occurring in a burst (burst errors) in the radio communication system, in Step S1004, the interleaver 15 performs interleaving for changing the order of the bit sequences in the transmission data containing the encoded bit sequences #A1 to #A9 according to a certain rule.
In Step S1005, the modulator 16 digitally modulates transmission data X (containing the encoded bit sequences #A1 to #A9) outputted from the interleaver 15, and then transmits the transmission data to a radio section.
Meanwhile, in the receiver apparatus 30, as shown in FIG. 2, the demodulator 31 converts a received signal into received data (a bit sequence) by demodulating the received signal in Step S2001.
In Step S2002, the deinterleaver 32 changes the order of the bit sequences in the received data that is the output from the demodulator 31 back to the original order of the bit sequences in the transmission data X according to a rule opposite to that adopted by the interleaver 15 in the transmitter apparatus 10.
In Step S2003, the error correction decoder unit 33 divides the received data (the bit sequence) outputted from the deinterleaver 32 into encoded bit sequences #A1 to #A9 in units that are the same as for the error correction encoding processing in the transmitter apparatus 10, and then performs error correction decoding processing.
In Step S2004, the connector unit 34 connects multiple encoded bit sequences #1 to #9 obtained by the error correction decoding processing. In Step S2005, the CRC checker unit 35 performs error detection processing (i.e. CRC check) using the CRC code added to the connected transmission data.
When no error is detected here, the receiver apparatus 30 transmits transmission acknowledgement information (ACK: Acknowledgement) concerning the received data to the transmitter apparatus 10. In response, the transmitter apparatus 10 transmits transmission data to be transmitted next.
On the other hand, when an error is detected, the receiver apparatus 30 transmits a retransmission request (NACK: Negative ACK) to the transmitter apparatus 10. In response, the transmitter apparatus 10 retransmits the same data as that previously transmitted.    Non-patent Document 1: “Digital Wireless Transmission Technology” written by Seiichi Sampei, Pearson Education
As described above, the ARQ processing is a technique useful for achieving high transmission quality of the radio communication system.
Nevertheless, in the case of real-time data transmission, the receiver apparatus 30 receives all the transmission data (bit sequences) transmitted by the transmitter apparatus 10, checks the CRC code, and sends a retransmission request. For this reason, there is a problem that transmission time is delayed depending on a radio environment.